Okay. Good afternoon shareholders and investors.

Welcome to our investor conference. First, I would like to report on our latest progress in security IP.

Over the past few years, our security IP has evolved from a foundational OTP and PUF into a PUF root of trust. Today, as security requirements for AI servers continue to rise, our technology has taken a major step forward, advancing from standalone security IP to the design of integration of comprehensive security subsystems.

This transition is crucial for us. We are no longer providing clients with just OTP, PUF, or root of trust.

We are now delivering fully integrated system-level security IP that combines encryption technology, software, firmware, and anti-tampering protections. In other words, our role within our clients' chips has become far more critical, allowing us to deliver significantly higher value.

Consequently, the potential license fee and also royalty are expected to increase significantly as well. We have licensed to several major global memory manufacturers to integrate our security IP into SSD, solid-state disk, systems for AI data centers, providing the security subsystems required to comply with Caliptra standards.

Beyond SSDs, we have also expanded into another vital area of AI servers, which is memory expansion IC. As AI models grow increasingly large, the memory capacity required by AI servers is surging rapidly.

As a result, CXL is becoming a dominant interface technology for AI server memory expansion. CXL switch and their related controller chips similarly require a complete hardware security architectures.

We are currently working with several CXL chipmakers to supply both security IP and security subsystems. Connecting the dots over the past few years reveal a clear trajectory for our security IP applications.

The last year we entered AI AGI CPUs and also BMC, and this year we expand into AI data center solid-state disk security subsystems, and now we are penetrating CXL switch for the AI server memory expansions. This means our security IP is expanding from a single chip inside an AI server to multiple critical chips.

Furthermore, many of these advanced chips are utilizing cutting-edge process nodes such as 3nm and generating much higher licensing and royalties than corporate average. Another highly favorable trend for us is Caliptra.

Driven jointly by global tech giants such as Microsoft, Google, Intel, AMD, and NVIDIA, we are seeing an increasing number of AI and data center chips and systems adopting the Caliptra security architecture. This indicates that the number of chips requiring root of trust security subsystem and the related security IP will grow significantly moving forward.

Therefore, we remain highly confident in the long-term growth of our security IP within the AI server and data center markets. Next, I would like to also share some updates on another key growth driver we are heavily focused on, which we call is the Logic Flash technologies.

Currently, our collaboration with foundries on Logic Flash technology is accelerating. Applications extend beyond embedded Flash to include standalone Flash products as well.

We believe the significance of Logic Flash goes far beyond adding another IP technology to our portfolios. More importantly, it presents an opportunity to leverage a more competitive process and cost structure to gradually replace portions of existing legacy Flash technologies.

Flash memory represents a massive market with exceptionally broad applications. Once Logic Flash enters mass production and begins progressively replacing conventional Flash technologies, the market opportunity and the long-term impact on our future revenue and profitability will be far-reaching.

For these reasons, we have a strong confidence in our multi-year growth outlook ahead. Next, I would like to invite our financial officer, Joseph, to present our second-quarter performance.

Thank you.

Good afternoon, everyone. Now let's begin with our 2026 second-quarter financial results.

The second-quarter revenue was NT$1,097 million, up 0.2% sequentially and up 17.1% year-over-year. Operating expenses were NT$431 million, down 0.3% sequentially and up 10.2% year-over-year.

In results, our operating income was NT$666 million with an increase of 0.6% sequentially and an increase of 22% year-over-year. Operating margin also increased by 0.2 percentage points sequentially and increased by 2.4 percentage points year-over-year to 60.7%.

Our net income, amounting to NT$580 million, experienced a decrease of 2.8% sequentially, but an increase of 44.9% year-over-year. The EPS for this quarter was NT$7.77.

Next, let's move on to revenue contributions by licensing and royalty. Licensing in the second quarter accounted for 39.2% of the total revenue, increasing 12.8% sequentially and up 35.1% year-over-year.

On US dollar basis, licensing grew by 12.8% quarter-over-quarter and 32.6% year-over-year. Royalty in the second quarter contributed 60.8% of our total revenue, decreasing 6.4% sequentially, but increasing 7.8% year-over-year.

On US dollar basis, there was a 6.7% decrease quarter-over-quarter, but an increase of 8.6% year-over-year. Overall, the revenue increased by 0.2% quarter-over-quarter and up 17.1% year-over-year.

On US dollar basis, the growth was 0.1% quarter-over-quarter and 16.9% year-over-year. For the first half of 2026, the licensing and royalty revenues are as follows: Licensing in the first half accounted for 37% of our total revenue, increasing 45.2% year-over-year.

On US dollar basis, licensing grew by 45.9% year-over-year. Royalty in the first half contributed 63% of the total revenue, increasing 7% year-over-year.

On US dollar basis, there was 9.8% increase year-over-year. Together, the total revenue for the first half increased by 18.5% compared to the previous quarter, and on US dollar basis, the growth was even stronger at 20.9% year-over-year.

With that, I will comment further on our revenue contribution by specific IPs. NeoBit accounted for 21.9% of total revenue in the second quarter.

The licensing revenue increased 11.2% sequentially, but decreasing 22.4% year-over-year, while royalty increased by 9% sequentially and increasing 9.2% year-over-year. For NeoFuse technology, they accounted for 56.6% of the total revenue in the second quarter.

The licensing revenue was up by 24.8% sequentially and up by 55.6% year-over-year. In terms of royalty, NeoFuse royalty decreased by 13.3% sequentially, but increased by 4.4% year-over-year.

For PUF-based security IPs, it contributed 10.9% of total revenue. The licensing revenue decreased 13.8% sequentially, but increased 133.5% year-over-year.

In terms of royalty, PUF-based royalty increased by 213.9% sequentially and increased by over 1,600% year-over-year. Lastly, for MTP technology, accounted for 10.6% of the total revenue in the second quarter.

The licensing revenue increased by 40.2% sequentially and increased by 9.3% year-over-year. The royalty from MTP was up 7.2% sequentially and increased by 19.2% year-over-year.

Together, for the first half of 2026, the revenue by technology are as follows: NeoBit licensing revenue decreased by 18.5% year-over-year, but the royalty increased by 2.4%, and together accounting for 20.9% of the total revenue for the first half of 2026. For NeoFuse, the licensing revenue increased by 37.9%, and the royalty also increased by 6% year-over-year, contributing to 58.2% of our total revenue in the first half.

For PUF-based security IPs, the licensing revenue increased by 264.6% year-over-year, and the royalty increased by over 1,300% year-over-year, and together accounting for 11.6% of our total revenue in the first half. Lastly, for MTP technology, the licensing revenue increased by 19.6%, and the royalty increased by 30.4% year-over-year, and together accounting for 9.3% of the total revenue.

Now let's take a look at our royalties for 8-inch and 12-inch wafers. First of all, 8-inch wafers accounted for 37.5% of the royalties, up 4.2% sequentially and up 1.2% year-over-year.

On US dollar basis, this represents a sequential increase of 4% and a year-over-year increase of 3.1%. For 12-inch wafers, it contributed 62.5% of the total royalties, down 11.9% sequentially, but increased 12.3% year-over-year.

On US dollar basis, this represents a sequential decrease of 12.1%, but a year-over-year increase of 12.2%. In total, 156 product tape-outs were completed in the second quarter, and we will provide more information in our management report, which will be released shortly after this earnings call.

Next, I would like to invite our Chairman Charles to share a little bit more about our future outlook. Thank you.

In the following section, I will address our future outlook. As far as licensing revenue concerned, licensing will continue its strong momentum due to robust demand for our technologies from leading edge to the legacy process node, security, and the next-generation Flash technologies.

For the royalty revenue, the royalty revenue growth is expected to accelerate, driven by the higher ASP from the new advanced node applications and the new application ramps, and also expanding the PUF royalty contribution and a growing mix of higher royalty rate of MTP-related applications. As far as new technologies, for the advanced node, OTP and PUF-based hardware security continue to develop and qualify next-generation OTP and PUF-based hardware security solutions for 2nm gate-all-around technology and also sub-2nm nodes and meeting a growing customer demand in the device identity, key protections, and secure boot, and also hardware root of trust.

Another new technology will be next-generation 1T-Flash. Our 1T NeoFlash technology is advancing across embedded and also standalone applications, and its logic process-compatible architecture offers greater scalability, lower process complexity, and better cost efficiency.

In the future outlook for the business development platforms, which we have five items. The first is chiplet security platform.

We continue to work with ecosystem partners on an end-to-end security framework for chiplet-based systems, covering supply chain traceability, identity, and authentication, and also secure provisioning, and also the die-to-die communication, and also the key management and hardware root of trust, addressing the increasingly complex security challenges of AI, and also the advanced packaging, and heterogeneous integration among today's geopolitical environments. The second item is data center security and Caliptra platform.

Targeting data center and AI servers, we continue to upsell, expanding PUF root of trust from hardware root of trust solution into a Caliptra-compatible security subsystem, and integration service that reduce integration complexity and accelerate customer deployments. Another business platform is on the AI compute and also root of trust platform.

We are extending collaboration across CPU, AI accelerator, and AI ASIC ecosystem to integrate chip-level root of trust, secure boot, device identity, and also secure key protection into the next-generation AI computing platform, strengthening trust and also security from silicon to system. Another business platform we are developing is HSM edge server and security-as-a-service platform.

The PUF-based HSM edge server combines device identity, key and certification management, and secure OTA updates, signature verification, and privacy protection, and post-quantum cryptography migration. Early opportunities are progressing in automotive OTA and PKI, and also HSM integration with potential to expand into industrial control and edge AI, smart device, medical, and also the data centers.

The last platform is we call it the post-quantum security platforms. We continue to strengthen our PUF PQC portfolio with attack-resistant hardware security, including side-channel protection to support the transition to post-quantum security standards.

Okay. Next, I would like to pass to Felix, our Head of Digital Marketing, to share with our feature topic today.

Felix, please.

Modern data centers depend on thousands of interconnected servers, each processing sensitive workloads, credentials, and proprietary data. System-level security ultimately begins much deeper, inside the silicon.

A server board contains chiplets of CPUs, accelerators, BMCs, networking, storage controllers, and other programmable devices. Each component loads firmware and communicates across shared interfaces, creating multiple points where trust must be established.

Without a consistent hardware root of trust, compromised firmware, counterfeit components, leaked keys, or unauthenticated communication can allow an attacker to move across the board and persist below the operating system. Caliptra addresses this challenge with an open-source root of trust architecture designed for data center-class silicon.

It establishes a standardized security foundation that can be integrated into each major system on chip. During boot, the Caliptra subsystem begins from immutable code, authenticates its firmware, measures the device state, and derives protected identities and cryptographic keys.

It can then support secure boot, signed firmware updates, and device attestation. However, the security architecture still requires a trustworthy physical source for device secrets, life cycle data, and entropy.

PUFrt provides this silicon-level foundation directly beneath the Caliptra core. Its PUF generates a device-unique secret without permanently storing the key.

OTP securely retains configuration and life cycle information, while the hardware noise source supplies high-quality entropy for cryptographic operations. With Caliptra deployed across critical devices, components can authenticate one another, verify firmware, establish protected channels, exchange keys, and produce evidence of their security state.

The result is board-level security built from independently verifiable chips, extending a consistent chain of trust from each component across the server platform and throughout the data center.

eMemory and PUFsecurity, your trusted partner in providing non-volatile memory and PUF-based security intellectual properties.

Hi, everyone. What you have just viewed in this video is one part of a much bigger movement happening around Caliptra and the hardware root of security.

Before I begin this talk, I'd like to briefly mention some related activities we've just been involved in. Earlier this week in Taipei, we participated in a Caliptra workshop focused on implementation and on bringing the specification closer to production silicon.

We also presented at two sessions at OCP APAC, where we discussed Caliptra and chiplet security from both the architecture and systems perspective. Those discussions reinforce something we've been seeing more broadly across the industry.

These security technologies are becoming increasingly important as AI servers and data center infrastructure become more distributed and more interconnected. Rather than covering everything around Caliptra, I'd like to use the next few minutes to just focus on the underlying reason why this movement is gaining momentum.

Instead of starting from security, I would actually like to start from how AI compute itself has been changing. AI systems are increasingly being built across multiple dies, accelerators, memory devices, and high-speed fabrics.

As more components are connected together, more of these components and their interfaces also need to be individually trusted and protected. That's the story I'd like to present today.

AI compute can no longer scale in a single die. When we talk about scaling AI compute, simply making chips larger is no longer enough.

In the past, if we wanted more performance, we could build a larger die or use more advanced process nodes. These are practical limits that we will approach, including die size, yield, cost, power, memory bandwidth, and I/O all start to become constraints.

Increasingly, the industry is scaling by composition. There are two important architectural trends shown on the slide, and I want to separate them because they're related, but they're not the same thing.

The first one is chiplets, which operate inside the package. Instead of building one enormous monolithic SoC containing every function, we can divide the system into multiple specialized dies.

For example, we have a CPU compute die, a GPU or NPU accelerator dies, we have management dies, a security die, or dies with other specialized functions. Importantly, these dies do not necessarily need to use the same process technology.

The compute portion may benefit the most from advanced node, but other dies such as management, security functions, it may be more economical on less advanced nodes. Chiplets give us modularity, reuse, better economics, and another way to continue scaling the processor package.

Even if we scale inside the package, we eventually hit another boundary, the processor socket and the server itself. That's where Compute Express Link, CXLs, come in.

CXL operates at the system level outside the processor package. Here you can see the servers on the left connected through a CXL fabric switch to a CXL Type 3 memory shelf on the right.

Instead of memory belonging permanently to one CPU socket, CXL allows memory and other devices to participate in a coherent fabric. That means memory can increasingly be expanded, pooled, shared, and dynamically assigned across systems.

You could think of it as chiplets scale the processor by combining multiple specialized dies in one package, whereas CXL scales a system by connecting processors, accelerators, and memory across the server. That's a very important shift for the AI infrastructure.

We are moving away from scaling only through one large piece of silicon and towards scaling by connecting many specialized resources together. This composition has security consequences.

Every new die, link, device controller, and firmware layer creates another place where trust has to be established. That brings us to the next architecture.

The same composability that gives us flexibility and scalability also creates a much larger attack surface. Let me separate this again to two architectural domains.

On the CXL side, we now have multiple endpoints joining a fabric, high-value memory moving across links, switches controlling connectivity, and a fabric manager potentially deciding how pooled resources are allocated. That introduces several different classes of risk.

For example, if the firmware of a highly privileged infrastructure component such as the CXL switch is compromised, the impact radius can be very large because now the attacker is not targeting only one endpoint. They may potentially manipulate connectivity, resource allocation, or the behavior of multiple devices in the fabric.

Another important area is DMA, direct memory access, which is in panel 5. DMA itself is a legitimate and very powerful capability.

The security problem is when a compromised or malicious device receives more access than it should have. If those permissions are not properly controlled, a device can potentially read or modify memory outside its authorized region.

In an environment where memory is pooled or shared, the consequence can become especially serious: data leakage across workloads or even between tenants. Inside the chiplet package, the security problem looks different, but the principle is the same.

Now we're dealing with multiple active dies communicating across die-to-die interfaces. A counterfeit or rogue chiplet can introduce an unauthorized component into the package or supply chain, severely affecting silicon identity and supply chain trust.

A malicious or unauthorized die can introduce hardware Trojans, manipulate transactions, leak data, or undermine the assumptions of the entire package. Recent chiplet security research specifically highlights malicious chiplets and hardware Trojans as major system-level threats.

Chiplets may also be attacked leading to key extraction and secret leakage, as shown in panel 4. If the root key or device secret is compromised, the consequence is much bigger than simply losing one piece of data.

An attacker may be able to impersonate the device or undermine the trust relationship built on top of that identity. I don't expect everyone to remember these attacks, but the key point is the trust boundary has expanded.

Security can no longer exist only at the board level or only around the CPU. What we increasingly need to know is this: Is the device or die authentic?

Did it boot trusted firmware? Can I trust the keys inside it?

Can I trust the communication between components? Can I prove that trust to the rest of the system?

This is why the root of trust increasingly has to move closer to individual silicons itself. This is where architecture such as Caliptra become very important.

Caliptra gives us an open-source security architecture for establishing a hardware root of trust in modern devices. There's an important distinction here between a digital root of trust architecture and the physical security foundation underneath it.

On the left, we have the Caliptra subsystem. Within the subsystem, the Caliptra core includes things such as the RISC-V processor, cryptographic functions, SRAM and ROM, mailbox, and the firmware responsible for implementing the security architecture.

Ultimately, all that digital security logic has to anchor itself to something physical in silicon. As you see on the right, there are three fundamental requirements for this physical hardware anchor, which we also call foundational security primitives.

First, a unique device secret, UDS. We need something unique to the individual piece of silicon that can establish device identity and support key derivation.

Second is a secure non-volatile storage. Security-critical information such as life cycle state, configuration, seeds, or other protected value needs to survive power cycles and remain protected from unauthorized modifications.

Third, a trustworthy entropy. All of the cryptography above this layer ultimately depends on good randomness.

If the entropy is weak or predictable, the keys derived from it can also become weak or predictable. Caliptra provides the architecture and framework for the root of trust, but the foundation of that trust still has to terminate in physical properties and protected state inside the silicon.

That is the physical security anchor, and those requirements actually match very naturally to technologies of hardware security that eMemory and PUFsecurity have already been developing for many years. This is where we move from the architecture to the actual silicon implementation.

For the UDS, unique device secret, we use NeoPUF. Rather than simply programming the root secret into conventional memory, NeoPUF derives device-unique information from the intrinsic physical characteristic of each individual piece of silicon.

That gives us a silicon-bound foundation for device identity and key derivation. For secure non-volatile storage, we have NeoFuse, our OTP.

NeoFuse provides protected storage for security-critical information such as life cycle values, seeds, configuration, or other persistent security assets. For entropy, we provide the physical noise source supporting the TRNG, true random number generator, giving the cryptographic system the randomness required for secure key generation and operation.

On top of that, we are extending this foundation to the post-quantum era through PUF PQC. Importantly, we view these IPs as different pieces of the same security foundation: identity, protected storage, trusted entropy, and cryptographic agility.

Together, these are the types of silicon-level primitives that a framework such as Caliptra ultimately needs in order to establish trust. Having the primitives is only part of the problem.

For our customers, the next question is how to integrate all these pieces into a complete, validated security system. This is where our strategy goes beyond selling individual IPs.

We start with PUFrt as the hardware anchor IP. Around that, we add post-quantum security capabilities.

Importantly, we have experience in integrating with Caliptra because from a chip designer's perspective, the difficult question isn't just, "Can I license a PUF?" The real question is, "How do I turn this specification into silicon that actually works?

How do I connect the hardware primitives to the Caliptra root of trust architecture? How do I validate the interfaces?

How do I shorten integration and verification time?" That is why we're moving towards a validated subsystem approach.

Once that foundation is available, the same security architecture can scale across accelerator boards, AI servers, rack-scale systems, and eventually data center infrastructure. What starts as a very small security block in silicon can ultimately become the trust foundation for a much larger computing platform.

That brings us back to where we started, this increasingly composed AI system. The trust must extend across every layer of the AI infrastructure.

AI infrastructure is becoming distributed across multiple layers. At the system level, CXL can protect data moving across a link through mechanisms for confidentiality, integrity, and replay protection.

Protecting the link does not automatically mean that the device on the other end should be trusted. That end still needs an integrity, trusted firmware, secure boot, and also needs to be able to prove its state through attestation.

The multi-die package follows similar principles. Each active chiplet may have its own identity, keys, firmware, life cycle state, and relationships with the other dies in the package.

Trust increasingly has to extend from the data center to the rack, to the server, to the device, to the package, ultimately down to the individual silicon. That's why our foundational IP is so important.

NeoPUF, NeoFuse, and our entropy source and PUF PQC may be physically small pieces of an overall AI system, but they provide some of its most fundamental security properties: a unique identity, protected state, trustworthy entropy, and cryptographic trust. PUFrt brings those capabilities together as a physical hardware anchor, while Caliptra provides the architecture that builds a root of trust on top of them.

As AI compute becomes more composable and more distributed, we believe security has to follow exactly the same direction. Trust must also become distributed, but it must remain anchored in silicon.

That is the role we see for eMemory and PUFsecurity's foundational IP: providing the silicon trust foundation that enables secure chiplets, secure CXL-connected device, and ultimately the next generation of AI infrastructure. Thank you for your time.

這一題應該大家都很關心。這個上季有說下半年權利金會明顯成長，那現在對這個展望是不是更有信心呢？Joseph 請回答。 是的，我們還是持續的很有信心，因為我們目前已經看到蠻多項這個先進製程的產品，包含是像 ADAS、AI 的加速器，那

SSD、網通以及其他的新產品都已經開始進入量產。那加上晶圓代工的這個報價其實持續的在漲價，那我們認為下半年的成長動能應該是會加速。謝謝。

Our first question is: In the previous earnings call, the company mentioned that royalty revenue was expected to grow in the second half of this year. Are you now confident in that outlook?

Joseph, please.

Yes, our outlook remains the same. We have already seen several advanced node products, including ADAS, AI accelerators, SSDs, networking, and other new products.

They begin to enter the mass production phase. In addition, with foundry wafer prices gradually increasing, we believe the growth momentum will continue to accelerate.

Thank you. 公司提到已經有不少

3 奈米客戶產品完全授權，那請問今年下半年是否有機會開始貢獻權利金收入？Joseph。 我們目前已經看到客戶這邊在

3 奈米已經有幾百片的一個量產，那這表示他們的產品已經成功了，那明年這個量以及權利金貢獻會更加的明顯。

The company has mentioned that a number of customers using 3nm technology have already been licensed or taped out. Could some of them be contributing to royalty revenue in the second half of this year?

Joseph, please.

Yes, we have already seen customers moving into mass production with several hundred wafers, and this indicates that their products have been successfully validated. The contribution is expected to become much more meaningful next year.

AI 資料中心帶動高壓電源架構的升級，比如說 400

伏、800 伏的 HVDC 跟新一代的 Power IC。請問公司是否已經開始受惠？Joseph。 那 AI 中心的這個電源架構的一個升級對力旺而言，那我們 IP 是會被整合到例如說像電源管理、電源控制以及相關的類比混合訊號的晶片中，那公司就會因此而受惠。那隨著電壓以及功率密度的提升，Power IC 對於這個精準的校正、參數的補償、那裝置的一個識別、可靠度的一個管理以及資安功能的要求都會大幅度的增加，那力旺也可以提供相關的 IP。例如說 OTP 可以用在這個類比參數的一個校正、trimming 跟這個電源控制設定以及產品的一個識別；那 MTP 的話可以用在這個需要多次更新的系統參數以及組態的一個設定。那目前客戶已經陸續進入這個量產的階段，那未來這個權利金的貢獻會持續的擴大。

AI data centers are driving upgrades in high-voltage power architecture such as 400V and 800V HVDC, as well as next-generation power ICs. Has the company started to benefit from this trend?

Which product lines would be the main beneficiaries? Joseph, please.

Yes, for eMemory, the upgrade of AI data center power architectures creates opportunities through our IP being integrated into power management, power control, and related analog mixed-signal chips. As voltage levels and power density continue to increase, for power ICs, they require much more precise calibration, parameter compensation, device identification, and also reliability management, and of course the security functions.

The related IPs we can provide mainly includes OTP, which is mainly being used for analog parameter calibration, trimming, power control setting, and of course product identification. For MTP, they can support system parameters and configurations setting that need to be updated multiple times.

Our customers have already started to move into mass production, and we expect the contribution to expand further in the coming quarters. Thank you.

可不可以分享權利金當中有多少來自先進製程？未來幾年是否預期這個比例會提升？Joseph。 我們以授權金的 NRE 佔比來看，目前這個先進製程的部分已經超過

50%。那這是因為我們單一的授權金的單價其實是數倍高於平均的這個 license 的單價，那未來權利金的貢獻也渴望這個明顯的提升。

Could you share how investors should think about the contribution from advanced node products to your royalty revenue today and how you expect that mix to evolve over the next few years? Joseph, please.

In terms of licensing NRE contribution, advanced node projects already accounted for more than 50%. This is mainly because the licensing fee for a single advanced node project is several times higher than average project licensing price.

Looking ahead, as these projects gradually move into mass production, we expect the royalty contribution to increase meaningfully as well.

Q2 權利金收入相較 Q1 下滑，可否說明主要原因？謝謝。 那我們第二季的權利金主要是對應代工廠在第一季的出貨。那第一季的部分，普遍成熟製程的產能利用率仍屬於一個低檔，那加上部分客戶有這個季節性的庫存調整。那在第二季的部分，我們已經看到這個整體代工廠的產能利用率來提升，那加上我們新應用已經開始持續進入這個量產階段，那後續還有這個代工價的一個上漲來帶動，那我們預期

Q3 以及下半年的權利金的成長可以加速。謝謝。

Royalty revenue declined in the second quarter compared with the first quarter. Could you please help explain the main reasons behind the decrease?

Joseph, please.

For our Q2 royalty revenue, they correspond to the foundry production in the first quarter. Overall, mature node foundry capacity utilization remained at a relatively low level in Q1, and some customers were also going through seasonal inventory adjustment.

Starting from the second quarter, overall foundry capacity utilization began to improve, while new applications started to enter mass production. Together with subsequent impact from foundry price increases, we believe royalty revenue is expected to accelerate in the second half of 2026.

Thank you. 隨著

2 奈米跟 Gate-All-Around 製程逐步進入量產，請問 NeoPUF 跟 NeoFuse 在先進製程上的競爭優勢是否進一步提升？那目前客戶導入的速度是否也比過去來得快？Charles。 隨著製程進入 2 奈米跟這個 GAA，晶片設計跟這個製造成本持續極高，客戶面對面積、功耗、可靠度以及符合安全標準的要求也更加嚴格。在這個情況下，那個 NeoFuse 跟那個 NeoPUF-based security IP 的競爭優勢會更加明顯。NeoPUF 可以在晶片底層建立每個晶片獨有的硬體身分，支援金鑰產生跟這個硬體信任根；那 NeoFuse 則可以提供可靠的 OTP 的儲存，用於晶片的設定，還有這個 code patch，還有 SRAM repair 等等。這些功能都能與先進製程整合，符合先進製程 SoC 對安全性、可靠性跟高良率的需求。與以往相比，我們確實看到更多的客戶更早開始討論這個安全的架構，然後參與評估的這個晶片應用數量也都正在增加。

As 2nm and GAA processes gradually move toward mass production, have the competitive advantage of NeoPUF and NeoFuse in advanced nodes become even stronger? Are customers also adopting this technology faster than they did last year?

Charles, please.

As process technologies move from 2nm and GAA, chip design and manufacturing costs continue to rise, and customers are placing even stricter requirement on area, power consumption, reliability, and compliance with security standards. In this environment, the competitive advantage of NeoFuse and NeoPUF-based security IP become even more apparent.

NeoPUF can create an unique hardware identity at the silicon level for each chip, supporting key generation and hardware root of trust. NeoFuse provides reliable OTP storage for chip configuration, code patching, and SRAM repair and other functions.

This capability can be integrated with advanced logic processes and support the security, reliability, and high-yield requirement of advanced SoC. Compared with the past, we are indeed seeing customers start discussion on the security architectures earlier, and the number of applications under evaluation is also increasing.

越來越多

PUF 客戶晶片應用進入量產，那公司如何看待未來授權金跟權利金比例結構的變化？Charles。 近年來的營運表現來看，我們的

PUF 在授權金跟權利金方面的成長非常強勁，因為這個大部分都是這個 advanced node 用在 security 上面的需求。那我們覺得這個當 AI 開始，現在 AI 才成長非常快，那我們認為這個 security 的趨勢才剛開始。

As more PUF license enter mass production, how do you expect the mix between licensing and royalty revenue to evolve? Charles, please.

Based on our operating performance in recent year, our PUF business has delivered very strong growth in both licensing and royalty revenue. We believe this trend is still in the early stage because due to the AI booming very fast, and now there are a lot of demands to secure the AI applications.

We believe that the license fee and also royalty due to the application of PUF will be increased. 好，請問

1T-Flash 客戶目前的進展如何？是否有機會在未來一年左右進入量產？ 目前那個 1T 的

Flash 已與多家晶圓代工廠合作進行平台開發跟驗證。各平台正依照開發計劃持續進行，有機會在明年看到客戶開始量產。

Could you share the latest progress with customers for 1T-Flash? Is there a possibility that it could start moving into mass production within the next year or so?

Charles, please.

For 1T-Flash, we are currently working with several foundries partners on platform development and verification. Each platform is progressing according to its development plan, and we may see customers begin mass production next year.

公司

security IP 過去已經導入了

AI CPU、BMC 等應用，今年又進步擴展到 AI data center SSD 跟 CXL。是否代表公司 security IP 正從 AI server 中的單一晶片逐步擴展到更多關鍵晶片？未來還有哪些應用具有較大的成長機會？Felix。 是的。隨著 AI server 架構持續升級，我們看到硬體安全的需求已經從特定功能逐步延伸到運算、儲存、資料傳輸及系統管理等不同環節。這也讓公司的 security IP 有機會進入更多不同類型的晶片。從今年上半年的授權狀況，也可以看到這個趨勢。相關的應用已涵蓋 CPU、儲存裝置、光通訊 IC、FPGA 及高速介面晶片等多個領域。這對我們來說呢，未來的成長不只是來自於更多客戶，而是 security IP 在整個 AI infrastructure 中的應用範圍持續擴大。同時我們在每顆晶片中能夠提供的安全功能也在增加。隨著 hardware root of trust、資料保護及系統級安全成為 AI infrastructure 的重要需求，我們認為 security IP 在 AI 與 data center 的市場會有非常大的成長空間。

Your security IP has expanded from AI CPUs and BMCs into AI data center SSDs and CXL-related applications. Does this suggest that eMemory's security IP is moving from a single chip to multiple critical chips within an AI server?

Where do you see the next major opportunities? Felix, please.

Yes. As AI server architectures continue to evolve, we are seeing hardware security requirements extend across different parts of the system.

These include computing, storage, connectivity, and system management. This gives our security IP opportunities to address a much broader range of chips.

Our licensing activity in the first half also reflects this trend, with applications across CPUs, storage devices, optical communication ICs, FPGAs, and high-speed interface chips. For us, the opportunity is not simply about adding more customers.

It's about expanding our security footprint across AI infrastructure, while also providing more security functionality within each chip. As hardware root of trust, data protection, and system-level security become very important for the AI infrastructure, we believe that there's significant room for our security IP business to continue to grow across AI and data center applications.

NeoFlash 是否會與 enterprise、consumer

SSD 使用的 NAND Flash，像 SLC、TLC、QLC 競爭？還是屬於不同的市場？Charles。 Standalone Flash 的開發首要的我們是以這個 NOR Flash 為主，所以跟這個 NAND Flash 屬於不同定位的記憶體技術。因為兩者主要解決不同的應用需求。NOR Flash 著重在於快速開機、低延遲、隨機讀取，還有 execution in place、XIP 及高可靠度，因此主要用於儲存 firmware 及系統的韌體。但是那個 NAND Flash 則是以這個高容量、低成本為主要的優勢，適合大型資料的儲存等應用。然而，現在等到代工廠順利量產這個 standalone NOR Flash 之後，未來我們才會再將 1T 的 Flash 拓展到 NAND Flash 的架構。

Will NeoFlash compete with NAND Flash used in enterprise and consumer SSDs such as SLC, TLC, or QLC, or does it address a different market? Charles, please.

For standalone application, our initial development focus is mainly on the NOR Flash. NOR Flash and the NAND Flash are two different memory technologies with a different positioning, and they mainly address different application needs.

NOR Flash is focused on fast boot, low latency, random read, and execution in place, or XIP, and high reliabilities. Therefore, it is mainly used to store firmware and the system code.

NAND Flash, on the other hand, is mainly designed for high capacity and the low cost, making it more suitable for the large-scale data storage applications. However, after foundry partners successfully move standalone NOR Flash into mass production, we may further extend 1T-Flash into NAND Flash architecture in the future.

2026 年 9 月歐盟的網際韌性法案即將全面強制執行。那資安法規要在落地的背景下，那公司有沒有看到這個

PUF 在先進製程 SoC 中的採用趨勢？Felix。 隨著這個網際韌性法案法規將正式強制實施，違規將面臨高額的罰款，且適用範圍涵蓋所有在歐洲市場銷售的聯網產品，市場對資安合規的重視程度持續提升。同時，secure by design 與 secure by default 的理念也逐漸成為產業的共識。在這樣的趨勢下，PUF 作為硬體信任根的關鍵技術之一，與裝置身分識別與金鑰保護中扮演核心角色。隨著法規要求日益嚴格，我們預期相關的安全機制的導入需求將持續上升。

As cybersecurity regulations such as the EU Cyber Resilience Act, or CRA, gradually come into force in September this year, how does the company view the adoption trend of PUF in advanced node SoCs? Felix, please.

With the CRA expected to become mandatory, non-compliance may result in significant penalties. The regulation also applies broadly to all connected products sold in the European market.

As a result, the market is placing great emphasis on cybersecurity compliance. At the same time, the concepts of secure by design and secure by default are increasingly becoming industry consensus.

In such a context, PUF, as a key technology for hardware root of trust, plays an important role in device identity and key protection. As regulatory requirements become more stringent, we expect demand for related security mechanisms to continue to increase.

請問公司

IP 有沒有切入一些太空通訊相關應用場景？請 Joseph 回答。 這方面我們的技術其實已經有被美國客戶用在低軌衛星相關的一些應用上。那由於這個低軌衛星是在非常嚴苛的這個太空環境下來運作，而且發射後基本上不太可能去回收去做這個

repair。所以 OTP 在這類應用中主要有幾個機制來提供相關的保障。那首先是抗輻射性以及這個高的可靠性。那太空中的這個強力輻射會使得傳統的 memory solution，例如說這個 Flash 或是 EEPROM 產生這個位元的翻轉，那會導致資料錯誤以及衛星的失效。那我們 OTP 是透過這個物理性的機制來改變電路的結構，那進而去儲存這個資料，所以一旦寫入就不會受這種輻射的影響，那其實是非常好用來存放這種關鍵的一些程式碼，例如說這個 boot code 那最安全的一個地方。那第二部分是安全通訊以及這個密鑰儲存。那低軌衛星作為這個龐大的網絡節點，那資安當然是非常重要。那 OTP 可以用於儲存這個加密的金鑰以及數位的憑證，那他們具備這個無法被遠端竄改或是抹除的一個特性，那其實是幫這個衛星以及這個地面站之間的通訊建立一個非常牢固的硬體信任根，那有效的去防止駭客的一個攻擊。那第三個部分就是這個硬體的身分識別。那面對成千上萬顆的這個衛星的一個星系，其實每一顆晶片在出場的時候都需要去寫入唯一的一個硬體 ID。那這對於這個星系的一個管理、故障的追蹤以及這個頻譜授權，這個自動化的驗證都是非常重要。那最後就是極端環境下的一個參數補償。其實面對這個太空劇烈的一個溫差，OTP 儲存這個精密感測器的校準以及補償參數，那可以確保衛星在極端的這個溫度、溫差的環境運作下，各項的這個電子訊號依然能夠保持一個良好的一個精準運作。謝謝。

Has eMemory's IP been adopted in application related to low Earth orbit, or LEO, satellites and space communications? Joseph, please.

Yes, our technology has already been adopted by US customers for low Earth orbit satellite applications. Given that satellites, they operate in extreme environments and are non-recoverable once launched, our OTP provides four critical safeguards.

Is radiation hardening and high reliability. Because in space, intense radiation can cause bit flips in traditional Flash or EEPROM solutions, and they can lead to data errors and mission failure.

Our OTP, on the other hand, they store data by permanently altering the physical circuit structure. Once written, they remain immune to radiation, making it the most secure place to store critical boot code.

Second is for secure communication and key storage. As satellites, they function as massive network nodes.

Cybersecurity is critical. Our OTP stores encryption keys and digital certificates that cannot be remotely tampered with or erased.

This establishes a robust hardware root of trust, protecting the communication between satellites and also the ground stations from hacking attempts. Third is hardware identification.

For a constellation with thousands of satellites, precise management is vital, and each chip should be programmed with a unique ID during production, which is essential for fleet management, fault tracking, and automated spectrum licensing verification. Lastly is parameter compensation for extreme environments.

Because as to withstand drastic temperature fluctuation in space, our OTP stores calibration and compensation parameters for precision sensors, and this ensures that electronic signals, they can remain accurate regardless of the extreme thermal conditions. Thank you.

In the interest of time, we will begin the last questions. 我想這個昨天早上公告，就是我們公司是被這個 MSCI 標準指數剔除。那加上這個公司的外資持股比例在台灣可能就正常的，就是 pure 真正的外資應該是僅次於台積電，大概 67%。那我相信大家投資人都會很關心，這個被指數剔除會不會造成大量的外部賣出？那公司是不是有什麼因應策略？好，那我就自己來回答。那這個事情那個因為我們都知道今年就是 AI 浪潮，所以很多股票是噴漲，在很短的時間漲了數倍。那我們不去 judge 這個 fundamental。那因為它標準指數的成分股是以市值排名，好像在賽馬一樣。所以每段時間就是你跑輸了就被剔掉，那其實是跟公司的基本面無關的。有人上去一年內又掉下來。那我們應該這樣講，我在 10 年前，我們在 10 年前不在 MSCI 標準指數的時候，我們外資持股就已經超過 50% 了，大部分外資呢到現在都還持有。甚至在今年 7 月底，就 7 月最後一天的時候，我們的外資持股是歷史新高。那我們可是它就是已經發生了嘛，OK？因為你沒辦法控制別人漲這種排名的市。那我們能做的就是我們去問了幾個我們持股比例高的大股東，那我們問他說：『那如果我們不在標準指數會不會去影響你的這個持股決策？』

那他們的回覆呢都說不會，因為他們雖然 benchmark 是 MSCI，但他們是主動判斷的，OK。那至於這個被動基金就是 ETF 調節，那根據過去的經驗，這類的指數成分股的變動，因為這個是個遊戲嘛，就是有計量方法是可以預測的。所以年初以來就外資券商或者是內資的 broker 就有預估說我們或其它公司會被剔除。所以呢事實上他們都會事先反應，不會到最後。所以你可以看到年初以來，到今天外資是在賣方，那有的是借券，借券就是等著最後一天去 block trade 給要賣的被動。那另外它我們是還有一個小型基金嘛，我們從標準組當到小型，小型它也會有個買盤。所以呢我們應該認為說它已經在發生了，OK？那你如果問我們說它會調節到什麼時候，其實我們也不清楚，因為沒人知道，好。那對我們來講一個 corporate 來講，我們能夠做的可能我們以前做的也是不夠，所以我們會更積極呢跟資本市場溝通，特別是內資。因為我們發現我們的外資都長線，他買了之後不動，我們就出現了一個叫流動性的問題。所以這也不見得是壞事，因為這個被動出來就是強迫增加 liquidity。那會非常積極的去參加法說，甚至於 OTC 針對散戶的 8 月有一場我也會去，如果是個人股東的話也歡迎你當場去詢問問題。那另外一個很重要的就是增加這個外資的報告。雖然很難懂也很難寫，但是就盡量讓更多人 cover，所以你在 information 的時候你就不會覺得說發生什麼事你不知道發生什麼事，波動那麼大。因為過去的波動主要是那個流動性不好，所以有人買有人賣那個波動就很可怕。那最最重要的呢我們非常非常深具信心，這個 10 年對我們來講最好的 10 年，所以我們未來會用這個基本面跟數字來證明公司的價值。以上。 Being removed from the MSCI index coupled with our relatively high foreign ownership may raise concerns about potential heavy foreign sell-off and how the company plans to respond.

MSCI index inclusion is primarily based on market capitalization ranking, and it's not a reflection of company fundamental. In fact, 10 years ago, when we are not including in the MSCI standard index, our foreign ownership of our shares already above 50%, and at the end of July this year, our foreign shareholder actually is a record high, like 67%, 68%, just slightly lower than the shareholding of the TSMC foreign shareholding.

We have reached out to our major foreign shareholder, and they response that the index adjustment will not affect their investment decision. As for passive fund rebalancing, experience showed that the index constituent change are largely predictable using quantitative model, the market usually discount and absorb the impact in advance.

The foreign selling pressure observed since early August likely reflect this passive fund adjustment. To mitigate significant stock price volatility, we will proactively enhance our communication with the capital market, especially local institutional investor.

We plan to participate in more investor conference and expand analysts research coverage to prove the company true value through our strong fundamental and operating results.

Thank you for attending our investor conference. For more information about our PUF-based security IP and the technology, we encourage you to visit our PUFsecurity website and check out our articles and other materials.

Thank you once again for your patience and the support for eMemory. We will continue to work hard on technology and IP innovation and PUF-based hardware security solutions for our customers and bringing higher returns for our shareholders.

Thank you.