Good afternoon, everyone. Welcome to eMemory's fourth quarter 2025 webcast investor conference.

Joining us today is our Chairman, Dr. Charles Hsu; President, Mr.

Michael Ho; Head of IR, Ms. Li-Jeng Chen; and Director of the Finance Department, Mr.

Joseph Hsia. The format of today's event will be as follows.

First, eMemory's Chairman, Dr. Charles Hsu, will give an opening remark.

Afterwards, our Financial Officer, Mr. Joseph Hsia, will present a review of our financial results.

Following that, President, Mr. Michael Ho, will share our business outlook.

Next, Dr. Charles Hsu will give a talk titled "eMemory's Technology Enables AI Memory Systems to Be High-Yield, Reliable, and Secure."

Then we will conclude today's conference with a Q&A section where our management team will answer your questions. Please feel free to submit your questions in the input box on the webcast window throughout the conference.

As a reminder, this conference is being recorded and a webcast replay will be available after the conference is finished. For more information, please visit the company's website under the Investor Relations section.

As usual, before we begin, we would like to remind everyone that today's presentation may contain forward-looking statements subject to risk factors associated with the semiconductor and IP business. Please refer to the cautionary statement on page 3 of today's presentation.

Now, I would like to give the floor over to eMemory's Chairman, Dr. Charles Hsu.

Okay. Good afternoon, everyone.

Looking back at the fourth quarter of last year, we achieved an impressive milestone with 18 licensing wins in the 3nm defense application. In the first quarter of this year, we expect to secure an additional 3nm license related to AI data center processors.

As this licensing progress, our PUF, physically unclonable function, royalties have moved into mass production, most notably with our PUFrt, which is a root of trust now integrated into the NVIDIA Vera Rubin architecture, and we expect royalty contribution to grow significantly in the second half of the year. The era of AI inference is transforming our industry.

We are seeing a surge in SRAM repair demand driven by computing-in-memory, alongside an urgent need for security in edge AI and physical AI. Looking further ahead, Google and IBM anticipate that quantum computing will be commercialized within 5 years.

As governments worldwide pivot toward post-quantum cryptography, PQC, we are entering the most significant hardware security upgrade in 25 years. We are uniquely prepared for this shift.

Our foundation is built on a proven track record: over 130 PUF-related tape-outs today, and also global reach of our technology—more than 700 process platforms worldwide are mass-producing wafers utilizing our technology. Also, our production is already a massive volume, and annual production record exceeding 9.8 million wafers, 8-inch equivalent.

This solid foundation is our most irreplaceable advantage as we integrate PUF into the global chip supply chain and establish a definitive hardware root of trust. We remain profoundly confident in the company's future.

Next, I would like to invite our Financial Officer, Joseph Hsia, to present our fourth quarter performance. After, our President, Michael Ho, will share our future outlook.

Thank you.

Hey, good afternoon, everyone. Now allow me to briefly go through our 2025 fourth quarter financial results.

Our fourth quarter revenue was NT$1.05 billion, up 10.1% sequentially and up 3.7% year-over-year. Our operating expenses for the fourth quarter was NT$413 million, increased 2.1% sequentially, but down 7.2% year-over-year.

Through ongoing org and process optimization, as well as AI transformation, we were able to improve our operational efficiency, and that led to our overall expenses remaining broadly flat despite continued business expansion. In result, our operating income was NT$636 million, with an increase of 15.9% compared to the previous quarter, and an increase of 12.3% year-over-year.

Operating margin increased by 3 percentage points sequentially, and increased by 4.6 percentage points year-over-year to 60.6%, reaching a record high, reflecting disciplined cost control and improved cost efficiency. Our net income amounting to NT$563 million, up 15.6% quarter-over-quarter and 9.4% year-over-year.

EPS for Q4 of 2025 was NT$7.54. Next, let's move on to revenue breakdown by licensing and royalty.

Licensing in the fourth quarter accounted for 33.1% of our total revenue, down 0.1% sequentially, but up 9.9% year-over-year. Royalties in the fourth quarter contributed 66.9% of the total revenue, increasing 15.9% sequentially and increasing 0.9% year-over-year.

For the full year of 2025, licensing increased 10.4% year-over-year, and royalties increased 5.1% YoY. With that, I will comment further on our revenue contributions by specific IPs.

NeoBit, it accounted for 22.5% of the total revenue in the fourth quarter. Its licensing decreased 25.5% sequentially, but increased 16.5% year-over-year, while royalty revenue increased 3.6% sequentially, but decreased 7.9% year-over-year.

Second, it is our NeoFuse technology. NeoFuse accounted for 58.5% of our total revenue in the fourth quarter.

Its licensing revenue decreased 22.1% sequentially, and 23% year-over-year, while royalty revenue increased 20.3% sequentially and 2.1% year-over-year. For PUF-based security IPs, it contributed 10.2% of our total revenue in the fourth quarter, mainly driven by licensing.

Licensing revenue increased 91.7% sequentially and 45.5% year-over-year, while royalty revenue accounted for less than 1% of the total royalties. Lastly, for MTP technology, it accounted for 8.8% of our total revenue in the fourth quarter.

Licensing revenue increased 4.7% sequentially and 29.8% year-over-year, while royalty revenue increased 13.6% sequentially and 49.9% year-over-year. For the entire year of 2025, NeoBit licensing revenue increased by 16.1% year-over-year, and royalty increased by 2.5%.

For NeoFuse, the licensing revenue increased by 0.7%, and royalty increased by 5.2% year-over-year. For PUF-based security IPs, the licensing revenue increased by 37.4% year-over-year.

Lastly, for MTP technology, the licensing revenue increased by 3.6%, and royalty increased by 21.7% year-over-year. Digging a little bit further into royalties breakdown by 8-inch and 12-inch wafers, for 8-inch wafers, it accounted for 36.2% of our royalties, up 3.3% sequentially, but down 10.5% year-over-year.

For 12-inch wafers, it contributed 63.8% of our royalties, up 24.5% sequentially and up 8.8% year-over-year. A total of 201 product tape-outs were completed in the fourth quarter, and we will provide more information regarding that in our management report.

Next, I would like to pass the floor to our President, Michael Ho, to share more about our future outlook. Thank you.

Thank you, Joseph. Good afternoon, everyone.

In the following section, I will address our future outlook. For licensing revenue, we expect strong growth, driven by increase in both the number of license and average license price across our foundry and fabless customers.

For royalties, growth is accelerating, driven by the ramp-up of mass production across various applications, higher ASP from the advanced nodes, additional PUF-related royalties, and higher royalty rates from the MTP-related IPs. New application ramp-up include: mobile, RFICs for US-based smartphone modem platforms; automotive, ADAS, networking-related applications, ISP, and LiDAR; cloud AI, BMC, SSD controllers, networking-related applications, CXL controllers and DIMMs; edge and endpoint, embedded controller for notebook and PCs, as well as security application for various smart devices, including printer cartridges, using the embedded PUF for anti-counterfeiting.

IP and security platforms: one, OTP, advanced GAA OTP IP development with leading foundries, extending towards sub-3nm nodes; RRAM, embedded RRAM platform with key foundries and IDMs for FinFET, BCD, and automotive applications; NeoFlash, deployment across foundries for BCD and mixed-signal process in 12-inch fabs; security IP, PUF-PQC achieved NIST FIPS 205 and SP 800-208 certification, reaching a milestone in comprehensive post-quantum cryptography protection. For security ecosystem expansion: chiplet security, end-to-end authentication and supply chain trust for advanced packaging; CPU platform collaboration, PUF-based security root of trust integrated with major CPU platforms; automotive and healthcare, PUF-based HSM SoC supporting secure OTA and privacy protection.

This concludes my comments. Next, I will pass the time to Charles.

Thank you.

Let's watch video first.

We often hear about artificial intelligence, AI. What does it really mean?

AI is built on two core processes: training and inference. Training builds the model.

Inference runs it in real time to make decisions. As AI enters everyday products, inference becomes the dominant workload.

Inference depends on constant, fast memory access. If memory is slow, performance stalls.

That's why many well-organized SRAMs placed close to compute, and achieving high bandwidth, is essential for efficient AI inference. Speed alone is not enough.

Reliability matters. If SRAM fails, data must be retried, rerouted, or repaired, slowing systems and creating risk.

From stalled robots, to autonomous driving and AI-assisted surgery, healthy memory is critical for safe AI. For years, eFuse was the standard SRAM repair solution, but AI inference has outgrown eFuse.

High current, routing congestion, large area, and limited repair capacity make eFuse unsuitable for modern AI chips. While eFuse supports only tens of kilobits, today's AI needs repair data at almost 100 times of that, at megabit scale.

Together with Siemens, eMemory's NeoFuse one-time programmable, OTP, memory delivers an effective SRAM repair architecture. eMemory's NeoFuse OTP stores repair information at high capacity and with high reliability.

Tessent detects SRAM faults, computes for optimal repair approaches, and then applies data remapping to repair. Adding a fuse box interface enables cross-talk between NeoFuse and Tessent.

Mechanistically, a two-phase validation approach maximizes SRAM yield. For phase one, NeoFuse OTP self-repairs to remain 100% defect-free.

For phase two, Tessent analyzes the SRAM array and assigns redundancy to defective cells. This creates a scalable, automated flow that keeps large SRAM arrays healthy and inference-ready.

With a significantly smaller footprint and true in-field repair, we have built a reliable foundation for production-scale AI. Longer chip lifetimes, fewer AI interruptions, our solution is built for real-world applications.

eMemory and PUFsecurity, your most trusted semiconductor IP company for NVM and security solutions.

Okay. As you can have seen in the video, this is just one clear example of how our IP can power AI in reliable and efficient manners, and particularly to overcome current pain point encountered by using current technology such as eFuse for AI implementations.

Thus, to follow, I would like to present to you a more comprehensive view of eMemory's technologies and how we can enhance reliability and security across various memory architectures. In today's AI-driven world, memory system face three critical challenges: achieving high yield at advanced process node, ensuring reliability under extreme workload, and maintaining robust securities.

EMemory addresses all three through our innovative logic NVM and the PUF-based security solutions. Let me walk you through how our technology enables the AI memory ecosystem from on-package memory all the way to same system-level storage.

As the heart of eMemory is our logic NVM technology, that is non-volatile memory built using standard logic fabrication processes. First, one-time programmable memory, we call it OTP.

This includes our NeoBit, mainly on 8-inch wafers for mature nodes, and NeoFuse, on 12-inch wafers mainly for both mature and also advanced nodes. OTP is programmable once and cannot be altered, perfect for storing permanent data.

The second is the multi-time programmable memory, which is MTP. Our NeoEE, NeoMTP, and NeoFTP solutions allow reprogramming multiple times, offering flexibility for firmware updates and also configuration changes.

The third is the flash memory, with our NeoRRAM and the NeoFlash product, providing the highest rewrite endurance for code storage and executions. Together, they can be used in wide range of critical applications.

For instance, we use OTP to repair defective memory cells in DRAM and SRAM, restore faulty pixels in image sensor, and trim analog circuit to meet specifications. This directly translate to higher manufacturing yield and lower cost.

For MTP and the flash, which enable on-chip code storage and also execution, eliminating dependency on external memory, they also support product version control and post-manufacturing customizations. For security applications, OTP provides the foundation for storing unalterable hardware key, the root of trust for any secure systems.

Once programmed, these keys cannot be modified even by sophisticated attacks. Compared to traditional non-volatile memory, logic non-volatile memory possesses several advantages.

In terms of manufacturing complexity, traditional NVM require 10 or more additional masks beyond the standard logic process. That is more than tens of extra manufacturing steps.

Our logic NVM, no additional mask needed, which make it dramatically simpler process. Those extra process steps in traditional NVM also mean longer manufacturing cycle and significantly higher costs.

Our logic NVM use the same equipment, comparable process flow, resulting a substantially lower cost. For complex process, it result in lower yield.

The traditional NVM suffers from this, and the logic NVM built on mature standard logic process typically maintains high yield even at advanced nodes. A shorter development cycle is also a major advantage of logic NVM.

Traditional NVM requires the development of a new transistor model, with extensive R&D and the lengthy testing before deployment. Logic NVM uses existing logic processes and model, which can be integrate and deployed rapidly without reinventing the wheel.

For the scalability is also critical for future implementation. The traditional NVM has limited expansion capacity due to requirement of new equipment investments.

However, logic NVM is highly expandable, no new equipment needed due to its logic process compatibilities. We have noticed major chip manufacturers are increasingly adopting logic NVM, and it is not just because it is better, it is also economically essential at advanced process nodes.

Now let me introduce our second core technology, which is PUF-based hardware security. PUF stands for physically unclonable functions, and in fact, our anti-fuse PUF, NeoPUF, was developed from our OTP and serves as the foundation of our security IP solutions.

Thinking of PUF as silicon fingerprint, just as no two human fingerprints are identical, no two chips produce the same PUF signature, even chips from the same wafer. This hardware key is essentially invisible to attackers, making it extremely difficult for them to extract or clone.

During the past 6 years, we have developed several security IP based on this foundation. For root of trust, our secure OTP store immutable data.

TRNG generates true random numbers. Combined with NeoPUF, our PUFrt IP provides chip-unique ID and keys, establishing hardware-anchored trust foundations.

By integrating with crypto processors, we offer PUFcc for cryptographic coprocessing, and PUFefsm for hardware security module, enabling secure key management and cryptographic operations. In terms of cryptography, we support a comprehensive suite of cryptographic algorithms: traditional standards like RSA, ECC, AES, and SHA, as well as PQC for post-quantum cryptography, and many others, providing complete cryptographic coverage for any security requirements.

Our solutions have achieved multiple critical certifications. For post-quantum cryptography, we have NIST CAVP certification covering FIPS 203, 204, and 205, plus SP 800-208.

For random number generation, we have also achieved NIST CAVP and the ESD verifications. For platform security, our solution are PSA Level 2 ready and Level 3 root of trust certified.

Additionally, we hold SESIP Level 3 certification for IoT security evaluations. This comprehensive certification portfolio ensure our solutions meet the most stringent security requirements across all major industries.

Altogether, this security approach that have been validated can provide in-depth defense network to secure modern systems. With our security IP in mind, now let me show you how our technology enables the entire AI memory hierarchies.

SRAM are the fastest cache embedded directly in GPU, TPU, and NPU of AI accelerators. At advanced nodes like 3nm and below, SRAM cells are extremely sensitive to manufacturing variations.

With the ability to repair defective SRAM, HBM, and DRAM cells, our OTP dramatically improves SRAM yield and lower the cost of the chips. For High Bandwidth Memory, HBM, are on-package 3D stacked DRAM, providing massive bandwidth for AI training and also inference.

HBM stack can be 8 or 12 or even 16 layers high. Since a single defect can compromise the entire stack, embedded memory repair ensure stack integrities.

Our OTP can endure thermal and also electrical stress, and thus guarantees long-term data memory retention and also operational stability under extreme AI workloads. For server DRAM include DDR6, 7, and the emerging SOC, advanced memory module, and DDR5 standards also benefit from our embedded memory repair solution by OTP, whereas our MTP enable flexible memory management for DIMM configurations.

In DDR5 and SOC advanced memory module standards, with this IP, we enable cost-effective AI chip mass production. When there are millions of AI server modules, a few percentage points of yield improvement translates to hundreds of millions in cost saving across the industries.

For CXL memory, which represents the future of data center memory architecture, where memory pooling and disaggregation happen at the infrastructure level. Since CXL memory pools are accessed by hundreds of servers, our PUFrt security solution is critical here.

Without proper security, data leakage become a critical risk. PUFrt enables multi-tenant data isolation, ensuring that when multiple customers share the same physical memory infrastructure, their data remains cryptographically separated.

For the storage memory, our PUF-based security solution protects data storage within NVMe and SSD controllers to safeguard AI models, which can be worth many millions in development costs and proprietary data. Lastly, let me reemphasize the key message here.

Our IP and technologies provided by our company, eMemory and PUFsecurity, are AI memory system enabling technologies. In summary, with our technology, AI memory system achieve three critical goals simultaneously.

First is the high yield, which is necessary for economic AI chip production at advanced nodes. The second is high reliability, which required for the AI inference workload in mission-critical applications.

The third is high security, demanded by the enterprise and cloud AI deployment with multi-tenant environments. This is what makes AI system truly scalable and deployable in production environments.

This is what I would like to share with you today. Thank you for listening.

Next, I will enter the Q&A sections.

Thank you, Charles. This concludes our prepared statement.

We will now begin the Q&A section. Please submit your questions in the input box on the webcast window.

All of our questions will follow the format of answering the Chinese version first, followed by the English version. We will now collect the questions and begin our Q&A section.

今天的問題非常多，我們會一一回答。好，第一個問題是：公司一直強調每年授權案都持續增加，不管是在晶圓廠越來越多的製程授權，或者是在晶片公司的設計授權，像一年就有

600、650 個，那 process

node 一年大概都有 100 多個。然後晶圓代工廠呢又一直在蓋廠。那這樣來說，我們的 TAM 不是一直在增加嗎？那合理上，我們的權利金收入應該要遠優於代工廠。那是甚麼樣的原因讓這樣的成長性還沒有看到？那這一題我們請 Joseph 回答。謝謝。 好，那其實 TAM 的擴大並不會即時等比例的反映在我們的權利金收入上，這兩者之間會存在一定的時間差。因為不管是晶圓廠這邊的這個製程的授權，或是晶片公司的設計授權，我們從簽約到設計導入，到客戶的產品量產，到最後反映到我們的權利金收入上，通常都需要比較長的一個週期。那尤其是在先進製程以及高複雜度的應用上，這個時程可能會拉得更長。那過去兩年，其實產業新增的產能以及成長動能就是高度的集中在先進製程，而我們相關的授權比較多還是處於在設計以及導入的階段，那尚未全面進入這個量產的放量期。我們在主要的代工廠 12 吋的滲透率大約是 1.4%，但是我們認為隨著已經累積超過 100 個 16 奈米以下的這個 tape-out，那慢慢進入這個量產的階段，未來對權利金營收成長貢獻的空間是非常大。

Our first question is, the company continues to highlight growth in foundry and designing license. With foundries expanding capacity and our TAM increasing, why hasn't our royalty revenue growth outperformed the foundries?

Joseph, please.

Yes. Actually, the expansion of TAM does not translate immediately and proportionally into our royalty revenue as there is an inherent time lag between the two.

Whether it is technology licensing to the foundry side or design licensing to the chip customers, the cycle from contract signing to design-in to customer mass production and eventually to our royalty revenue recognition typically takes time, and especially for advanced nodes and more complex applications. Over the past 2 years, while industry growth was concentrated in advanced nodes, many of our licenses were still in the design and integration phase and had not yet reached high-volume production.

Currently, our penetration rate among major foundries' 12-inch capacity is around 1.4%, and to date, we have built a solid pipeline with more than 100 tape-outs at 16nm and below, and these designs will gradually move into mass production, and we do see meaningful room for further royalty revenue growth. 聯發科跟高通呢都在最新的法說提到，手機，特別是手機，還有一些消費性應用，因為記憶體價格上漲，會壓抑需求。請問這樣的趨勢對公司的影響為何？我們請

Michael 回答。 好，確實因為記憶體價格大漲會影響到一些中低階手機的銷售。那我們今年來自美國手機大型客戶的營收，主要會受惠於這個

content 的增加，那包括像 modem 模組相關晶片的導入。另外像 wafer 單價的提升，比如說像 PMIC 由 0.13 micron 會轉向 55 奈米，OLED 的 DDI 也會從 28 奈米轉向更先進的 16 奈米。另外還有像折疊手機的 driver IC 它的用量會從原本的一顆提升為兩顆。另外，手機的銷售即使不好，但是銷後市場事實上會更好。銷後市場的 DDI 這是剛性的需求，即使消費者不更換整機，只要進行面板的更換，這也要同步更換 DDI IC。那綜合以上的因素都會抵銷終端需求疲弱所帶來的一個影響。謝謝。

Given the rising memory costs that MediaTek and Qualcomm cite as a headwind for consumer demand, how does eMemory view this potential impact on overall business performance? Michael, please.

This year, the revenue contribution from a major US smartphone customers have primarily benefit from the increased content per device, including the following factors: one, increased content from the modem-related chips, driven by broader adoption across the modem modules; two, migration to more advanced process, with PMIC moving from 0.13 micron to 55 micron, and OLED driver IC transition from 22 28nm to 16nm, resulting in higher ASP per wafer; three, higher DDI contents driven by foldable smartphones, where the number of display driver ICs has increased from one to two per device. Furthermore, we also benefit from a natural hedge in the aftermarket.

Even when new smartphone sales slow down, the demand for replacement panel remains robust. Because every panel replacement require a new DDI, this inelastic demand allow us to offset any weakness in the new device market and maintain a resilient revenue base.

Thank you. 以

NVIDIA 新一代的平台，比如說是 Vera Rubin，強化 confidential computing 跟硬體信任架構為例。那個 CES 這個 Jensen 就講得很清楚，這是一個 hardware security landing，真的

landing 的開始。那公司目前在此類平台中的 design-in 跟商業化進展，可不可以分享多一些？Joseph 回答，謝謝。 其實在 NVIDIA 的這個 Vera Rubin 架構中，以 Caliptra 硬體信任根導入 rack-scale 級別的機密運算其實開始成為這個核心的一個設計。那這也反映出產業正在進入近 20 年來相當關鍵的一波硬體安全結構性升級。那隨著 Agentic AI 對於資安的要求大幅的提升，那安全的機制其實也不再只是一個外掛的附屬功能，而是直接被納入晶片底層的一個架構，成為系統設計中非常重要的一個基礎。有了 Caliptra 的保護，那像 OpenAI 啊、Anthropic 這樣子的模型開發商才敢放心的將他們價值數十億美元的模型部署到第三方的雲端平台上，因為他們知道就是即使是在別人的機器上運行，那這些 model 的一些細節跟權重也只有自己的代碼可以解開。在這樣子的架構下，我們已經導入了多項的晶片。那隨著我們和全球主要的雲端服務供應商的合作持續的深化，在次世代的 Caliptra 2.0，我們的 security IP 可以支援相關平台在硬體信任以及機密運算上的一個需求。加上推論對於 SRAM repair 的剛需，我們認為我們在 AI server 的滲透率會有更大的一個提升。

Using NVIDIA's next-generation platform such as Vera Rubin as a example of the industry's move toward confidential computing and hardware security architectures, could you share more insights into its design-in progress and commercialization timeline in this area? Joseph, please.

Yes. Within NVIDIA's Vera Rubin architecture, the integration of Caliptra as hardware root of trust for rack-scale confidential computing has become a core design.

This actually reflects a pivotal, once-in-two-decades structural upgrade in hardware security. As agentic AI demands significantly higher security, protection is no longer an optional add-on, but a fundamental element integrated directly into the silicon architecture.

With the protection provided by Caliptra, model developers like OpenAI and Anthropic can securely deploy their multi-billion dollar models onto third-party cloud platforms, because they can trust that even on external servers, their model weights remain encrypted and accessible only to their authorized codes. We have already secured multiple design wins within this framework.

As we deepen our collaboration with global CSPs, our security IP will support evolving requirements for hardware trust and confidential computing in the upcoming Caliptra 2.0. Combined with the essential demand for SRAM repair in inference chips, we do expect that our penetration within the AI server market will continue to expand.

Thank you. 現在已經量產的

3 奈米客戶應該是沒有用公司的

IP，因為沒有看到 3 奈米的權利金。那我們如何去預期未來的 3 奈米會有應用導入？那是基於甚麼樣的原因？請 Michael 回答。 目前已經量產的 3 奈米產品通常是高度客製化的 SoC，那一般客戶為了盡快進入市場，通常會沿用前一代的設計。但是接下來的 3 奈米應用會因為更複雜的設計和安全性的要求，那客戶會傾向使用經過驗證、可快速導入跟整合型的這個 IP，然後能夠符合系統級需求的這種 security IP，那這個部分就會是我們的一個優勢。謝謝。

Given that 3nm products currently in mass production have not yet contributed to royalty revenue, how should we think about adoption trajectory at 3nm going forward? What are the key drivers that support future penetration?

Michael, please.

It's common for the initial wave of 3nm SoCs in mass production to utilize design legacy from previous generation, as customers prioritize a fast time to market. However, we are seeing a clear shift for the next wave of 3nm applications.

As designs become increasingly complex and security requirements more stringent, customers are moving toward proven, pre-validated, and highly integrated IPs. They need system-level security solutions that can be seamlessly integrated into their advanced architectures.

This is precisely where our competitive advantages lies, offering the silicon-proven security foundation that reduce design risk and accelerate deployment for our customers. 請問公司後量子加密客戶導入的進度？我們請

Joseph 回答。 好，那公司目前推出的

PUF-based PQC 硬體安全解決方案已經通過了 NIST FIPS 205 以及 SP 800-208 的認證。那涵蓋的是這個，例如說金鑰交換以及數位簽章等關鍵的應用。那代表我們相關的技術已經完整的對應到 NIST 目前所定義的核心 PQC 規範，那已經具備這個實際導入以及商業化的基礎。那在應用進展的方面，相關 PQC 的解決方案已經獲得多家伺服器相關的晶片導入，那用來支持他們符合 NIST 標準的後量子資安需求，那作為高安全等級系統中硬體信任架構的一個部分。謝謝。

Could you share an update on customer adoption progress for post-quantum cryptography solutions? Joseph, please.

Yes. Our PUF-based PQC hardware security solution has successfully met NIST FIPS 205 and SP 800-208 standards.

It covers critical applications such as key exchange and digital signatures, and our technology now fully complies with NIST currently defined core PQC specifications and is ready for commercial adoption. In terms of application progress, our PQC solutions have already been adopted by several server-related chip customers, and these designs utilize our IP to meet NIST-compliant post-quantum security requirements and serving as a critical component of the overall hardware root of trust within the high-security systems.

Thank you. 公司提到後量子加密會帶動公司

secure solutions 的需求，那這類的 secure

solutions 是不是也有本土化的趨勢？比如說美國他希望用美國的 IP 業者，那中國也希望用中國的業者。這也請 Joseph 回答。 其實商用電子產品的銷售一直都是全球性的，那這代表 security 應用必須使用同一個標準，資訊才可以互通。那目前 security 演算法的標準主要是依循這個美國國家標準技術研究院，就是我們所謂的 NIST 的規範。那我們 PUF-based 的 security solutions 提供很高安全性的硬體安全，那我們在美國、中國也都有蠻多客戶。那這也是為甚麼他們的產品一直都是銷售到全球，然後應用我們的 IP。謝謝。

We've discussed how post-quantum cryptography will drive demand for our security solutions. Do you foresee a trend toward localization in this field where, for example, the US mandates the use of domestic IP providers while China does the same?

Joseph, please.

Yes. Regarding the localization of security solutions, it is quite important to note that commercial electronics are part of the global market.

For data to be interoperable across borders, security applications must adhere to the same unified standards. Currently, the global benchmark for security algorithm is primarily set by NIST in the US, and our PUF-based security solutions provide high-integrity hardware security that aligns with these international standards.

This is why we have a robust customer base in both the US and China, because their end products are designed and ultimately sold into the global market. Thank you.

請問公司能不能詳細說明跟

DARPA 的協議？如果

DARPA 採用 eMemory 的解決方案，那 DARPA 供應商是不是也會採用這些方案？如果是，那 eMemory 會不會把握這樣的機會？Joseph 請回答。 是的。因為當我們的技術被納入 DARPA 的專案當中的時候，代表我們的解決方案已經在非常高安全等級的系統中完成實際的一個驗證，包含硬體信任根的建立啊、金鑰保護啊，以及系統整合等關鍵的要求。那這類的專案通常會形成一套可供參考的安全設計範本，那讓相關的這個系統供應商以及生態系內的夥伴可以在後續的專案中進行評估和導入。那實務上，這些供應商在規劃例如說像國防、航太以及其他高安全基礎設施的相關產品的時候，往往會優先參考已經通過 DARPA 驗證的這個技術架構，來降低他們這個設計以及驗證的風險。謝謝。

Could you please provide a detailed explanation of your agreement with DARPA? If DARPA adopts eMemory solutions, will DARPA suppliers also adopt these solutions?

If so, how does eMemory proceed with such business opportunities? Joseph, please.

Yes. When our technology is adopted within DARPA programs, it indicates that the solution has undergone practical validation in high-security systems, covering key requirements such as hardware root of trust, key protection, and system integration.

These programs typically establish reference security design frameworks that enable relevant system suppliers or ecosystem partners to evaluate and consider for their subsequent projects. In practice, when these suppliers plan products for applications such as defense, aerospace, and other high-security infrastructure, they often prioritize architectures that have already been validated through existing DARPA programs, and this would help reduce both of their design and qualification risks.

Thank you.

請問最近很熱門的光通訊，CPO，會不會用到公司的

IP？請 Joseph 回答。 會。那我們已經有客戶在 4 奈米的晶片中導入相關的應用，那也有近期被產業中領導廠商所併購的新創客戶，他們也已經導入我們相關的一個 solution。那隨著資料傳輸的速度提升到 800G 甚至是 1.6T 以上，那光電轉換對精準度的要求其實變得非常的高。那在半導體和 CPO 的應用當中，OTP 其實更像是一個晶片的身分證以及校準的資料，用來確保說每一個晶片在系統裡面都可以正確的去運作。那我們認為 OTP 之所以在 CPO 的應用下不可或缺有幾個主要的原因。那第一個當然就是這個精密的校準，因為每一顆矽光子晶片在生產的時候都會有一些微小的差異，那我們透過 OTP 來儲存雷射功率以及波長的校準參數，可以確保每一個晶片都能達到它們最佳的這個傳輸效能。那第二個就是安全以及防偽。CPO 在 AI 資料中心其實是一個非常高價值的組件，那我們 OTP 可以提供唯一的識別碼，就是我們所說的 unique ID 以及 Secure Boot 的功能，能夠有效的防止這個硬體被偽造，那確保說正品執行的安全性。那第三點是自動組態的設定。那 CPO 模組內其實也包含其他複雜的元件，那我們 OTP 可以記錄硬體版本以及預設的參數，例如說是等化器的設定，那讓這個系統在開機的時候能夠自動的去識別設備，並且完成最佳化的傳輸設定，那會大幅簡化整個系統整合的難度。那最後當然是比較直觀的節省空間以及高可靠度。CPO 的封裝空間其實極度受限，那相較於傳統需要額外的外附 EEPROM，我們的 OTP 直接整合在晶片的內部，那不僅大幅的節省了封裝的空間，那也讓資料更具不可竄改的這個可靠性。

Regarding the trending topic of CPO, referred to co-packaged optics, will your IPs be required for these types of optical communication solutions? Joseph, please.

Yes. We already have customers adopting our solutions in 4nm chips, and we also have startup customers that were recently acquired by industry leaders who have also adopted our solutions.

As data transmission speeds accelerate to 800G and even 1.6T, the precision required for optical-electrical conversion becomes extremely high. In the field of CPO, our OTP acts as both a digital ID and a precision calibration profile.

There are four core reasons why our OTP is essential for CPO from our point of view. First is precision calibration.

Since every silicon photonic chip has a slight manufacturing variance, our OTP stores laser power and wavelength parameters to ensure that each chip achieves their peak transmission performance. Second is security and authentication.

CPO modules are high-value components for AI data centers, and we provide unique IDs and secure boot solutions that will prevent hardware counterfeiting and also ensure the integrity of firmware execution. Third is optimized configuration.

CPO modules contain multiple complex components, and our OTP records hardware revisions and default parameters such as equalization settings, allowing the system to automatically recognize and optimize device upon startup, which will significantly reduce the system integration complexity. Last is the space efficiency and reliability.

Space is extremely limited in CPO packaging. Unlike traditional external EEPROMs, our OTP is integrated directly into the chip, and this not only saves critical board space, but also ensures data remains permanent and tamper-proof.

Thank you. 根據這個

NVIDIA 的

Jensen 講，晶片迭代速度從過往的 2 年變成 1 年，那這對公司的影響是正面還是負面？Joseph 回答。 這對我們而言其實是比較正面的趨勢。因為我們提供的是 hard IP，這類 IP 通常是需要通過這個製程的驗證才可以提供給 fabless 客戶使用。那以往 foundry 最先進的製程的晶片，要動用我們 IP 認證完其實都會來不及，所以我們都需要等前一個製程的客戶 migrate 導入。那現在這樣 migrate 的速度增加，表示換 IP 的機率也大增，那下一代轉入的時間也會加速。那此外，現在也可以用這個 chiplet 的方式，比如說最主要的 compute die 是用最先進的 2 奈米製程，但是我們的 solution 可以導入我們已經 qualified 過的 3 奈米的 chiplet，然後再用先進封裝的方式去導入這個主晶片。謝謝。

According to Jensen Huang, chip iteration cycles have shortened from 2 years to just 1. Is this trend a net positive or negative for the company?

Joseph, please.

This is actually a very positive trend for us. As a provider of hard IP, our solutions need to be process-qualified before it can be adopted by fabless customers.

In the past, for chips manufactured on the foundry's most advanced nodes, completing our IP validation in time for the first wave designs was often quite challenging. As a result, adoption typically occurred when customer migrate from the previous process node.

Now, as customers' migration cycles are accelerating, the likelihood of their IP replacement also increases, and the transition to the next generation can also happen faster. In addition, with chiplet-based architectures, even if the compute die moves into the most leading-edge nodes such as 2nm, our IP can be introduced earlier through a 3nm chiplet and integrated into the main system via advanced packaging.

Thank you. 請問公司跟

Arm

合作的進展為何？Charles 請回答。 我們和 Arm 的合作已經從過去單純的 IP 授權逐步擴展到更廣的技術合作。在技術面上，我們持續讓自己的硬體信任根和 Arm 架構下的安全模組與參考設計接軌，主要是為了因應邊緣 AI 和雲端資料中心在機密運算上的實際安全需求。同時在先進製程上，我們也持續整合 OTP 與 PUF 的技術來支援整個系統層級的安全設計。

Could you update us on collaboration with Arm? Charles, please.

Our cooperation with Arm has evolved from a pure IP licensing model into broader ecosystem collaboration. On the technical side, we align our hardware root of trust with Arm-based security subsystems and reference designs to support confidential computing in edge AI and cloud data centers.

At the same time, we continue integrating OTP and PUF technologies on advanced nodes platform to meet system-level security needs. 公司有沒有

ASIC 客戶已經導入公司的

IP？那主要應用是在哪個領域？請 Michael 回答。 是的。我們公司已經有多家的 ASIC 客戶導入我們的 IP，相關的專案已經進入先進的製程，並且應用在 AI 的像加速晶片、CPU、ISP 和一些像高速介面如 SerDes 等的設計，那對應到 AI、HPC 等高效能的應用場景。那此外，我們也透過跟 ASIC 設計服務夥伴的合作，持續擴大相關 IP 在先進製程平台上的導入跟應用。謝謝。

Do you have any ASIC customers currently integrating our IPs? What are the specific applications?

Michael, please.

We have successfully secured multiple ASIC design wins, with several key projects already moving into advanced nodes. Our IPs are being integrated into critical designs such as AI accelerator, CPU, ISP, and high-speed interface like SerDes, specifically targeting high-performance applications in AI and HPC.

Furthermore, we continue to expand adoption and application of our IPs across advanced process platforms through strategic collaboration with our ASIC design service partners. This collaborative approach allows us to scale our presence and capture the growing demand in the high-end application market.

Thank you. 美國要求晶片本土化製造，對公司一直是中國跟台灣為主代工廠為主，這樣是不是不利？請

Joseph 回答。 其實授權我們技術的代工廠以及

IDM 是遍布全球的，並非只有中國和台灣的代工廠而已。那不論是美國本土公司，或是主要的晶圓代工廠在美國都陸續有這個生產基地，也都會使用我們的 IP。那隨著先進製程以及安全相關平台的需求提升，那我們認為這對我們來說是相對有利的。謝謝。

In the context of global supply chain realignment, how does the company view future business opportunities with Chinese foundries and their overall contribution? Joseph, please.

Actually, our technology is licensed to foundries and IDMs worldwide, and extending far beyond just China and Taiwan. Both US domestic semiconductor companies and major global foundries with manufacturing sites in the US utilize our IPs.

As the demand for advanced nodes and security integrated platforms continue to surge, we do believe this broad geographical presence position us favorably to capture these growth opportunities. Thank you.

市場上還有哪些公司有提供相關的

secure IP？那跟他們的競爭力比較為何？Joseph 請回答。 其實除了我們之外，另外還有三家主要的 security IP 的公司，那分別是 Rambus，以及透過併購這個

secure IC 進入這個市場的 Cadence 以及 Synopsys。那 Rambus 以及 Cadence 的強項是在他們加密軟體層以及協議，那我們則是專注在硬體物理層的安全基礎。所以在很多案子和應用場景裡面，他們其實是我們的潛在客戶。那 Synopsys 併購了 SRAM PUF 業者 Intrinsic ID 之後也進入這個市場。但是相較於 SRAM PUF，我們的 NeoPUF 最顯著的優勢是在於物理層的穩定性以及可靠度，那並且符合 Caliptra root of trust 的硬體標準。由於 NeoPUF 不需要額外的這個 Error Correction Code 或是儲存這個 helper data，那這樣子的 OTP 能顯著的簡化系統的架構，並且具備這個優異的抗輻射性。那這樣子的特性使得我們的 PUF OTP、TRNG 和 root of trust IP 都可以非常高階、非常高等級的安全應用具備這個非常強的競爭力。

Who are your main competitors in the security IP market, and how does your competitiveness compare to theirs? Joseph, please.

Yes. When looking at this landscape, we see three other main players who are Rambus, Cadence, who entered the market through the acquisition of Secure-IC, and Synopsys.

For Rambus and Cadence, they do excel in the software encryption and protocols, whereas we focus on hardware physical layer. Because of this, our roles are often complementary, and in fact, they are our potential customers.

For Synopsys, and there is SRAM PUF technology. Our NeoPUF offers a clear advantage in terms of physical stability.

We are fully aligned with Caliptra hardware standards, and most importantly, our NeoPUF doesn't require complex error correction or helper data. By eliminating these extra requirements, we can significantly simplify the system architecture.

Combined with our radiation-hardened reliability, our PUF-based security IPs remain the top choice for high-security applications. Thank you.

TSMC

縮減成熟製程產能，對公司的影響是不是就直接少掉這個市場？Joseph。 其實我們認為主要的晶圓代工廠現在是有計畫的在進行這個產能的調整以及調配，而不是單純的去縮減這個成熟製程。那一些晶片客戶本來在這些主要代工廠生產，那可能會因此去轉到比較先進的製程，例如說像我們觀察到 PMIC 已經部分從 8 吋轉到 12 吋，或是他們會委託其他的這個晶圓廠來承接這個量產。等於說這樣的一個調整對客戶產品的量產其實影響不是太大，那對我們的業務以及 royalty 其實是沒有實質的影響。那我們同時認為這樣的一個產能調整也能讓成熟製程的供需結構比較健康，那晶圓代工的價格反而可以往比較有利的方向去發展。謝謝。

TSMC is reducing its mature node capacity. Does this mean we are losing that market segment entirely?

Joseph, please.

Yes. We observed that foundries are engaging in a strategic reallocation of capacity rather than a simple reduction in the mature node capacity.

Many customers are migrating to advanced platforms because of this. For example, we're seeing transition of PMIC from 8-inch to 12-inch wafers or leveraging other fab capacity.

This shift has no material impact to our customers' production or on our business. In fact, we do believe that this kind of disciplined capacity management actually helps stabilize the supply and demand for mature node capacity, ultimately will foster a more favorable pricing environment for us.

Thank you.

那最近成熟製程的代工價是否有調漲？那公司怎麼看這個代工價格的趨勢？Joseph。 其實隨著主要代工廠去調整他們的產能配置，縮減部分這個成熟製程產能，我們委託確實有從一些客戶那邊聽到一些成熟製程調漲的聲音。不過當然實際的情況還是要看各家代工廠的這個定價策略啊，以及他們的產能利用率。相較於前一段時間成熟製程的價格下滑，目前的價格趨於穩定，甚至出現部分回升。所以整體來看，認為對我們的權利金貢獻是偏正面的。謝謝。

Has there been recent price hike for mature nodes? What is our outlook on foundry pricing?

Joseph, please.

Yes. As major foundries adjust their capacity and tighten supply for mature nodes, we are actually hearing from our customers about potential increase of mature node wafer price.

However, the extent of such price adjustment will depend on specific foundries' pricing strategy and also their utilization rates. Compared to the previous period of price erosion, the current trend of price stabilization and potential recovery is actually quite positive for our royalty revenue from our point of view.

Thank you.

PUF 是否在可預期的未來會成為市場主流？相對於現在的 secure solution，那 PUF 解決了甚麼問題？有機會讓晶片非採用不可嗎？Charles 請回答。 PUF 的功能是作為 unique ID 跟那個密鑰的用途。除了在 AI 加速器、data center 的 security 應用之外，在未來 edge AI 跟那個 physical AI 的發展扮演必須的角色。因為在未來世界裡面是一個 autonomous 的世界，每一個 autonomous 的物件都要有一個 unique ID，而且都要有自己的密鑰來保護自己的資料跟資產。

Will PUF become the market mainstream in the foreseeable future? Compared to current security solutions, what specific problems does it solve that make it a must-have for chip designers?

Charles, please.

Our PUF technology serves as unique ID and secure key. Beyond its current role in AI accelerators and data center security, it is becoming essential for the expansion of edge AI and the physical AI.

As we move toward an autonomous world, every autonomous device will require an unique identity and its own cryptographic keys to protect both data and access. We are providing the foundation of trust for this future.

最近市場很擔心這個整個軟體產業會被這個

AI

工具取代，IP 產業同樣也是高毛利，是不是存在類似的情形？Joseph。 其實我們認為 IP 產業和純軟體服務其實不太一樣。那當然 AI 的確正在改變設計以及開發的流程，但是在半導體 IP 的領域，其實真正的核心價值是來自於我們發明的 IP，以及底層的這個電晶體技術。那這部分當然是受到專利權保護。那再加上長時間累積的製程 know-how、矽驗證的經驗，以及和晶圓廠以及客戶之間的深度合作，那這些都不是光靠 AI 工具就可以輕易取代。那對我們來說，AI 其實比較像是幫助我們把研發做得更快，那把驗證做得更有效率的一個工具，而不會直接去取代我們的 IP business。那隨著製程持續往更先進的節點發展，對 IP 在可靠度、良率、功耗以及這個安全性的要求當然也越來越高。那這也更依賴實際量產經驗和平台化的一個能力。所以我們認為 AI 不但不會削弱 IP 產業的長期價值，反而會讓真正有製程深度、量產實績的 IP 公司跟其他競爭者的差距拉得更開。謝謝。

As AI tools are reshaping the software industry, do you see any comparable impact or structural change emerging in the semiconductor IP industry? Joseph, please.

Yes. We believe that the IP industry is fundamentally different from pure software services.

Regarding AI, we see as an enabler instead of a disruptor. While AI can optimize workflow, it cannot replicate our core value, which is the invention of the underlying transistor technology.

Our moat is built on patented innovations, and also decades of process know-how, and the silicon-proven track record. These are the foundational assets rooted in the long-term trust and physical engineering.

These are the things that AI tools alone cannot simply replace. As we move into advanced nodes, the requirements for things like reliability, for yield, for security will become even more stringent.

This increases the industry's reliance on actual mass production experience and also platform-level expertise, which creates a significant barrier to entry. That being said, rather than diminishing the long-term value of the IP industry, we actually believe AI will further widen the gap between companies with proven silicon success and those without, and it will strengthen our competitive moat.

Thank you.

In the interest of time, we will begin the last questions.

請問公司所推動的改革措施，目前已經觀察到有哪些具體成效？Joseph。 其實我們認為改革的成效最終當然還是要回到看這個營運效率和財務的獲利結構是不是有真的變好。那這一年來，公司持續的在做調整這個成本結構以及優化營運的流程，那主要是讓我們的經營可以變得更有彈性、韌性，以及更有效率。那也可以降低這個外部環境波動帶來的影響。那在營收方面，只要整體的代工價格可以趨於穩定，不再持續的下滑，以我們目前的業務組合來看，本身就可以支持相對穩定的一個成長。那同時在我們內部的營運上，我們透過流程優化以及費用控管，去年這個年度的營業利益率已經提升了

3.4 個百分點，那這裡可以看到我們的改革已經相對有效的反映在我們的獲利表現上。在這樣的基礎上，隨著營運的效率持續改善，加上本身公司就是一個高毛利、低資本支出的一個營運模式，那我們認為獲利成長具備一定的結構性槓桿。所以整體來看，我們會持續的用財務紀律以及營運效率作為檢視我們改革成果的一個主要指標。謝謝。

Could management share what tangible results have been observed from the recent transformation initiatives? Joseph, please.

Yes. We believe our transformation must be reflected in measurable financial results.

Over the past year, we have focused on optimizing our cost and processes to build a more resilient, flexible, and efficient business that can better withstand market volatility. On the revenue side, as long as the foundry pricing remains stable and avoids further declines, our existing business mix is well positioned for steady growth.

On the operational side, through ongoing process improvements and cost discipline, our operating margin actually improved by 3.4 percentage points last year, and this indicates that our transformation is successfully translating into tangible profitability. With high margins and low CapEx, our business model is built for operating leverages.

As we scale, we do expect efficiency gains to drive stronger earnings while maintaining financial discipline throughout our transformation. Thank you.

We will begin the closing comments. Charles, please.

Thank you very much for coming to our investment conference. For more information about our PUF-based security IP and the technology, we encourage you to visit our PUFsecurity website at www.pufsecurity.com and check out our articles and other materials.

Thank you again for your patience and the support for eMemory. We will continue to work hard on technology and IP innovation, and the PUF-based hardware security solution for all customers and bringing a high return for our shareholders.

Thank you.

Thank you, ladies and gentlemen. Please be advised that the conference recording will be accessible within the next three hours.

Thank you, everyone, for joining us today. We hope you will join us again next quarter.

You may now disconnect. Goodbye and have a good day.